Join a passionate R&D team to develop the market-leading EDA tool for standard cell layout automation and optimization, to accelerate the Schematic -> GDSII workflow of standard cell design and enablement of the DTCO methodology.

Responsibilities:

1. Research, design, and development of the algorithms for standard cell layout automation, including device placement, intra-cell routing and DRC cleanup
2. Apply and encode different design rules into algorithms and archive process porting automatically.
3. Support planner and FinFET processes
4. Develop, debug and maintain the software production written in C/C++, and deliver it to customers with high-quality

Requirements:

1. MS/PhD in Computer Science, Electrical Engineering or Mathematics, or equivalent industrial experience preferred
2. Experienced in IC physical design, with good knowledge in DRC and LVS.
3. Skill in 1+ programming languages, good ability for algorithm implementation and testing. Solid background in data structures and algorithms.
4. Good communication skill and teamwork spirit.

Preferred Experience:

1. Experienced in standard cell layout design, optimization and verification
2. Working or developing experience related to mainstreamed APR tools and physical verification tools
3. Experience in Commercial C/C++ software development and testing
4. Knowledge of machine learning and multiple objective programming

Working conditions:

1. Official employment

2. Official salary, bonuses

3. VHI with dental care

4. Cell phone and internet compensation

5. Professional development in an international company