St. Petersburg, Moscow, other locations

Syntacore – semiconductor IP company creating customizable microprocessor cores, technologies and software tools based on RISC-V ISA, founding member of RISC-V International.

Our clients and partners are key companies from US, Asia, Europe and Russia, developing computational platforms, storage systems, personal and smart devices, including high-performance heterogenous multi-core systems with complex specialization and ISA extensions manufactured using latest technologies up to 5nm.

We are active member of conferences and working groups on RISC-V standardization and open-source projects. Our open-source SCR1 core published under permissive license became one of the most popular RISC-V processor GitHub projects.

Responsibilities:

• Analyze and improve efficiency of our compilation and/or programming, debugging, profiling tools
• Develop processor and system simulation models with RISC-V processor family starting from embedded microcontrollers up to high-performance super-scalar cores
• Design compiler and software optimizations targeting RISC-V ISA and specialized extensions

Practical skills:

• Experience with С/C++ and scripting languages (python/bash)
• Basic compiler, programming tools, and/or simulators knowledge
• Experience in Linux development environment
• General understanding of CPU uarch
• Experience with performance analysis and/or reverse engineering
• Contributions to open-source projects
• Any practical experience within RTL hardware design is a plus

Theoretical knowledge desired:

• Advanced compiler design & algorithms knowledge
• Modern operating systems knowledge
• Other CS university courses: Graph theory, Formal language theory

What we offer :

• Flexible working hours
• Challenging tasks in friendly environment
• Professional and career growth
• Conferences/publications opportunities for interested parties